In image processing, a dynamic random access memory (DRAM) is commonly used for storing source image data, which is then used for image processing when a subsequent motion estimation/compensation circuit accesses the DRAM. Note that a bandwidth of the DRAM is rather valuable. Supposing the motion estimation/compensation circuit frequently accesses the DRAM for the source image data, an overall performance is lowered due to latencies of the DRAM. Therefore, the prior art provides a plurality of line buffers between the DRAM and the motion estimation/compensation circuit, wherein the line buffers are generally realized using static random access memory (SRAM).
Reference is made to FIG. 1 showing a block diagram of a prior image processing circuit 100. As shown, line buffers 120a˜120g sequentially receive and buffer image data bit streams outputted from a memory 105. For example, when the line buffer 120g receives and buffers every pixel data of the first scan line of the image data bit stream, the line buffer 102f receives and buffers every pixel data of the second scan line of the image data bit stream, and so forth. A motion estimation/compensation circuit 140 reads data of image blocks as needed from the line buffers 102a˜102g, thereby avoiding performance degradation resulted from frequent accesses to the memory 105. However, when there are a large number of line buffers or when an overall storage volume needed by the line buffers is large, circuit cost as a whole is increased.